Today's integrated circuits include a vast number of devices. Smaller devices and shrinking ground rules are the key to enhance performance and to reduce cost. As FET (Field- Effect- Transistor) devices are being scaled down, the technology becomes more complex, and changes in device structures and new fabrication methods are needed to maintain the expected performance enhancement from one generation of devices to the next. The mainstay material of microelectronics is silicon (Si), or more broadly, Si based materials. One such Si based material of importance for microelectronics is the silicon-germanium (SiGe) alloy.
There is a great difficulty in maintaining performance improvements in devices of deeply submicron generations. Therefore, methods for improving performance without scaling have become of interest. One general approach for improving performance is to increase carrier (electron and/or hole) mobilities in FETs. A promising avenue toward better carrier mobility is to modify the semiconductor that serves as raw material for device fabrication. It has been known, and recently further studied, that tensilely or compressively strained semiconductors have intriguing carrier properties. In particular, improvement in the electron mobility has been achieved in a strained silicon (Si) channel NMOS as described in U.S. Pat. No. 6,649,492 B2 to J. O. Chu entitled “Strained Si Based Layer Made By UHV-CVD, and Devices Therein” incorporated herein by reference. Similarly for hole enhancement, compressively-strained SiGe have yielded high hole mobilities. Germanium (Ge) also has attractive hole carrier properties. It is for this reason that the SiGe alloy is an advantageous material for hole conduction type devices. The band structures of Si and Ge, and of the SiGe alloy, as well, are such that the hole transport, primarily hole mobility, improves if the materials are under compressive strain. Combination of tensilely and compressively strained SiGe regions in the same wafer is described in U.S. Pat. No. 6,963,078 to J. O. Chu “Dual Strain-State SiGe Layers for Microelectronics”, incorporated herein by reference.
Strained-Si layers may be the results of biaxial tensile strain induced in silicon grown on a substrate, which substrate is formed of a material whose lattice constant is greater than that of silicon. The lattice constant of germanium is about 4.2% greater than that of silicon, and the lattice constant of a silicon-germanium alloy is roughly a linear function of its germanium concentration. As a result, the lattice constant of a SiGe alloy containing fifty atomic percent germanium is about 2% greater than the lattice constant of silicon. Epitaxial growth of silicon on such a SiGe substrate will yield a silicon layer under tensile strain. In general, if the epitaxial layer has a smaller Ge concentration than the underlying layer and its thickness is less than the critical thickness, the epitaxial layer is under tensile strain, and conversely, if the underlying layer has a lower Ge concentration, the epitaxial layer is under compressive strain.
Ideally, one would like to have integrated circuits such that the electron conduction type devices, such as NMOS, are hosted in a tensilely strained Si or SiGe material, while the hole conduction type devices, such as PMOS, are hosted in a compressively strained Ge or SiGe material. (MOSFET stands for Metal Oxide Semiconductor Field- Effect- Transistor, a name with historic connotations meaning in general an insulated gate Field- Effect- Transistor, while nFET or NMOS and pFET or PMOS stand for n and p type MOSFETs.)